1. Field of the Invention
The field of the present invention relates generally to integrated circuits. In particular, the field of the invention relates to dynamic control for matching of impedance using on-chip components over a high-speed data link or transmission line. A dynamic control circuit enables matching of on-chip impedances with tighter tolerance than the impedance properties inherent in the integrated circuits due to manufacturing process variations.
2. Background of Related Art
There is an increasing need for a system that enables a portable, low power device, such as a cell phone, PDA, or the like to transfer data reliably via a USB (universal serial bus) interface directly to a host device, such as a printer, digital camera, MP3 player or the like without having to use a PC as a middleman. Although many devices currently support USB, generally such devices do not have the ability to act as hosts. Design of a host circuit requires impedance matching on-chip in order to match the driver to transmission line. An off-chip impedance matching results in an increased number of IC pins that is undesirable. Signal distortions resulting from impedance mismatches between input/output (I/O) buffer circuitry of the communicating devices, and the transmission line impedance can be significant.
On-chip components—such as resistors can vary due to fabrication process variations in the integrated circuitry of the devices. Semiconductor processes typically result in components having actual resistance values that differ from the nominal design value within a statistical range. That is, a resistor designed to have a nominal resistance of 75 ohms may end up having an actual resistance ranging from 60 ohms to 90 ohms, a +/−20% variation due to variation in the resistivity (sheet resistance) of the semiconductor material on which the resistor is fabricated. When the element value is critical to the operation of the circuit, such variation may adversely affect the I/O impedance and degrade performance of the circuit.
For optimum performance a high-speed data transmission circuit, such as one capable of utilizing USB, requires a close match between the termination impedance of the circuit and the impedance of the transmission line to which the circuit is coupled. Too much variation in the termination impedance due to variations in the manufacturing process may result in unacceptable performance, such that some integrated circuits are unusable.
Accordingly, various designs for I/O buffers have been proposed to match the output impedance of the I/O buffer with the transmission line impedance. Without proper impedance matching, overshooting, undershooting, and signal distortion can occur, particularly in high-speed data transfer.
One approach for controlling output impedance described in U.S. Pat. No. 6,429,685 attempts to achieve matching impedance using an operational amplifier to control the conductance of a three terminal semi-conductor device such as an FET, CMOS, or bi-polar transistor. This approach has the disadvantage that offset and bias currents of the operational amplifier can cause drift of the output impedance due to temperature changes. Also, this approach requires added complexity to stabilize a reference voltage. Otherwise, any noise on the reference voltage causes cyclical variation of impedance over time. That is, impedance will vary with the noise signal that appears at the reference voltage terminal resulting in loss of transmission signal integrity. In addition, this design integrates a slew-rate controlled driver as well as an impedance control in one circuit that is very application specific and is not a general impedance control method.
Also, conventional approaches as exemplified by U.S. Pat. No. 6,429,685 teach that digital on-chip impedance control techniques have many disadvantages including using discrete steps which generate high frequency components and produce problems with electromagnetic interference (EMI). See column 1, lines 37–43.
Therefore, what is needed is an on chip or integral system for reliably matching I/O impedance to enable data transfer from one peripheral device to another over a USB interface without first connecting the device into a compatible PC to download files, then uploading files from the PC onto the new device. There also is a need to provide improved compatibility among components in an integrated circuit used for an I/O buffer for high-speed data transfer between different devices in general. This need becomes critical when there is a wide range of manufacturing process variation, such as varying sheet resistance.
Other conventional solutions typically incorporate the use of off-chip components to implement matching termination networks. However, such solutions disadvantageously can use up a large number of IC pins and board space.
Other on-chip solutions require the use of separate test I/O pads for determining suitable impedance matching. For example, one external test pad is typically used to determine the suitable pull up circuit impedance, and a separate additional test pad is used to determine suitable impedance matching for the pull down circuit of the output buffer. Thus, separate external impedance calibration resistors are used for each I/O buffer section. The use of additional test pads and external resistors has disadvantages of increased board density and surface area, reduced reliability and increased cost.
One approach, for example, as disclosed in U.S. Pat. No. 6,064,224, by Esch, et al., describes an on-chip impedance matching network using up down counters that are always changing by small amounts. Therefore, pull up and pull down impedances are always changing by small amounts. This is reflected in small voltage changes across the load connected to the output of the FET network. This in turn adds another component of noise in the system attempting to regulate pull up and pull down impedance. A single FET network between the pull up and pull down driver switches includes two parallel sections for determining impedance of the pull up and pull down drivers, respectively, when pull up and pull down switches are closed. Due to the parallel connections of the first and second sections, the impedance of the pull up driver affects the impedance of the pull down driver, and these values are not independent of one another.
In another approach, (A new impedance control circuit for USB2.0 transceiver, Kyoung-Hoi Koo; Jin-Ho Seo; Jae-Whui Kim, ESSCIRC 2001. Proceedings of the 27th European Solid-State Circuits Conference, 18–20 Sep. 2001, Villach, Austria) digitally controlled transistor arrays are used as impedance elements as opposed to passive resistors. Such implementation does not result in an impedance that is linear over voltage range and also suffers from extra parasitic capacitance making it unsuitable for very high-speed applications.
In order to meet the demand for low-cost, high-speed serial data communication, CMOS technology is being widely used for high-speed serial data links. To improve data transmission speed in CMOS technology, various types of drivers have been proposed for better signal integrity.
In another conventional solution, current-mode differential CMOS drivers use differential switches to pull down the drive signal (while resistors are used to pull it up). However, with the increased use of scaled-down CMOS technology, the speed of a transmitting device is limited by large parasitic capacitance present in the drain area of the driver transistors, bonding pad, and electrostatic discharge (ESD) protection The same problems arise in the receiver side-parasitic capacitance and inductance in the I/O pad distort the received signal.
Therefore, what is needed is an improved system and method for dynamically matching impedances without resorting to transistors and which enables tighter control over impedance variations without regard to differing sheet resistance of individual circuit components.